Logic Analyser Usage Advice

[Rob Jarratt]

> -----Original Message-----
> From: cctalk <cctalk-bounces at classiccmp.org> On Behalf Of Paul Berger via
> cctalk
> Sent: 26 March 2021 11:54
> To: Rob Jarratt via cctalk <cctalk at classiccmp.org>
> Subject: Re: Logic Analyser Usage Advice
> 
> 
> On 2021-03-26 6:08 a.m., Rob Jarratt via cctalk wrote:
> > I have an old HP 1630G logic analyser. I am trying to use it to debug
> > a problem with an 82C206 peripheral controller (or rather I think
> > damage between the CPU and the peripheral controller). I am not very
> > experienced with logic analysers and I wonder if I am using it correctly.
> >
> >
> >
> > What I am trying to do is see which internal registers are being
> > read/written and the values. To do this there are two signals (XIOR
> > and
> > XIOW) that trigger the read/write on their rising edge. So I have
> > connected the XIOR and XIOW signals to the J and K clock inputs and
> > set the LA to clock on the rising edge. I have then told the LA to
> > trigger on a particular address range (in the State Trace screen if
> > anyone is familiar with this LA).
> >
> >
> >
> > When I run the analyser it complains of a slow clock. This makes
> > sense, because I am using the read/write signals to drive the clock
> > inputs so that I only capture actual reads and writes to the peripheral
> controller.
> > However, I don't seem to be getting sensible values in the trace and I
> > am wondering if the LA is really not capturing anything because of the
> > slow clock?
> >
> >
> >
> > I don't think it makes sense to clock the LA on the actual clock
> > signal because I won't be able to capture the address and data values
> > on the rising edge of the read/write signals and I would end up with
> > traces full of useless data.
> >
> >
> >
> > Am I doing it right, or is there a technique that I am missing here?
> >
> >
> >
> > Thanks
> >
> >
> >
> > Rob
> >
> I think you are the right track, If you wish to only capture register accesses
> you may want to qualify on the -ACK signal as the datasheet says it must be
> high for register access.  I would also clock on the rising edge  of the -XIOR
> and -XIOW signals as the data sheet seems to indicate that data is not valid
> on the falling edge.

Yes, I am using the -ACK signal too as part of the address and clocking on the rising edge of -XIOR and -XIOW. I wonder if the logic analyser itself might be faulty because I have set it to trigger on -ACK=1 and XA0-9=08X(hexadecimal, X=don't care), but I get XA values that do not match the trigger. I am wondering if it is problem with sampling too late after the rising edge maybe?

Regards

Rob