PDP-11/70 debugging advice

[Fritz Mueller]

Hi Josh,

ZAP is effectively reset for the micro-architecture, forcing the ucode address to known/initial value.  It has multiple sources throughout the processor, including tendrils into some of trap handling hardware. (Caveat: my experience is based off extensive work with the '11/45, but the micro-architecture as I understand it for the '11/70 is quite similar.)

For the '45, there was a very handy "KB11-A,D Maintenance Manual", which explained the logic of such internal signals and the board by board internal operation of the CPU to a very useful level of detail; I'm sure similar is available for the KB11-B,C?  It's worth a read through if you haven't already, though its quite a bit to take in.

I would imagine the next step would be to throw the RAC board out on extenders, verify that ZAP is asserted, and if so pursue the driving source.

Do you know if you have a KB11-B or C?

Happy hunting!

   --FritzM.