(V)HDL Toolsets

[Chris Hanson]

On May 23, 2020, at 7:54 AM, Jay Jaeger <cube1 at charter.net> wrote:
> 
> I don't think a 100K character IBM SMS machine needs DDR.  8D   For my
> old student ECE ZAP machine, I just used very simple
> on-development-board RAM, with a layer in between.  Probably do the same
> here.

These days, the RAM on a lot of development boards is DDR or something else that requires a significant amount of controller work.

> Ethernet might be nice, but I don't think I'd include a whole IP just to
> get that

I think it depends on whether you want to expose *Ethernet* to the device you’re implementing, or just to provide access to it *over* Ethernet. Exposing serial and other channels via SPI or I2C is certainly straightforward.

> probably just use I2C or SPI to an external micro controller
> (for lamps, switches, the console selectric, etc.)  Doing this would
> also help me fit to a smaller FPGA.

Of course, there are also IP blocks for I2C and SPI, some of which may again map to dedicated hardware on the FPGA, providing more room for your logic.

So yes, context matters, but you need to look at both what you want to accomplish *and* what the tooling and FPGA you’re using can provide.

Why do more integration work than you have to when you can focus on the interesting stuff?

  -- Chris