VHDL / IBM SMS Data gathering and HDL Synthesis Update

[Jay Jaeger]

MicroBlaze is free with Vivado and the Digilent Nexys4 I am using has a
Xilinx Artix 7 XC7A100T on it, which allows one to use Vivado for free
on it, via a WebPack license (The free WebPack license is restricted to
certain chips.)

https://www.xilinx.com/products/design-tools/mb-mcs.html

https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html

(WebPack is the license I am under) which includes the IP integrator
(allowing one to place a MicroBlaze processor into a project)

And, since version 2016.1, the Xilinx SDK (which has the standalone OS
for MicroBlaze, C compiler, etc.) has no additional licensing requirements.

https://www.xilinx.com/support/answers/71607.html

Finally, there are, apparently, some open source clones fo MicroBlaze:

https://en.wikipedia.org/wiki/MicroBlaze#Clones

JRJ

On 6/15/2020 7:37 AM, Tom Uban wrote:
> Very cool!
> 
> I know of MicroBlaze, but always thought it wasn't free?
> 
> --tom
> 
> On 6/14/20 4:25 PM, Jay Jaeger via cctalk wrote:
>> Don't know if anybody much cares, but:
>>
>> The HDL synthesis aspect of the SMS data gathering / HDL synthesis
>> application is coming along.  I can now handle:
>>
>> - Oscillators (using a counter divider)
>>
>> - Delay lines (using a shift register, so limited to a reasonable number
>>  of FPGA clock clock cycles, so, say 200 ns is not unreasonable (20 bit
>> shift register at 100 MHz).
>>
>> - Recognition and consolidation of individual signals into a "bus" when
>> generating groups corresponding to a group of individual ALD sheets.
>> (The individual ALD sheets use the individual signal names as they
>> appear on the sheet).  A simple database table associates a given
>> individual signal with a bus, and identifies the bit in the bus that
>> corresponds to the individual signal.
>>
>> So, I have not generated the IBM 1410 main oscillator, its main logic
>> clock and its I Ring - used to control instruction decode.  I have
>> synthesized the logic clock into an FPGA and run it (with a slowed down
>> 1410 oscillator so I could see what was going on.)
>>
>> Also, a word about VHDL - and the Xilinx Vivado.  While GHDL is useful,
>> I have found that Vivado is not slow at editing and *simulation*.  Silly
>> me - I got in the habit of synthesizing stuff before I tested it under
>> simulation - partly because I didn't know any better at first.  Vivado's
>> waveform viewer has some advantages (and disadvantages) compared to what
>> is available for GHDL.
>>
>> I have also started exploring a piece of "intellectual property" I can
>> use - MicroBlaze - to allow my generated system to talk to my PC, via
>> TCP, for things like lights and switches.  (Kind of like how the Amdahl
>> machines used to use first DG Novas, and later little UNIX systems for
>> their consoles, giving them access to the internals of the machine.)
>>
>> I knew MicroBlaze existed, but now I have actually played with it a bit
>> -- still learning.
>>
>> https://en.wikipedia.org/wiki/MicroBlaze
>>
>>
>>
>