A tale of two Automated Logic Diagram Sheets

[Jay Jaeger]

I encountered my second missing Automated Logic Diagram (ALD) page for
the IBM 1410:  13.64.03.1, which, based on the signals fed to it and
which it produces, would, fortunately, necessarily have the same logic
as page 15.41.10.1 - "E CH FULL CONTROL-ACC".  Page 13.64.03.1 is for
the second, or F Channel.

The E Channel version uses 9 NAND gates and 4 drivers.  However, based
on the card location chart, the F Channel version, even though it would
have corresponding logic, has TWENTY-ONE gates (some of those could be
just load resistors) on card type DGR.  These are ALL just INVERTERS.
The card location chart also calls out 2 gates on card type DFS - also
inverters, and one gate on card type AEK which uses equation (NOT IN1)
OR IN2 to produce its output.

The F channel logic used up two cards slots plus parts of six others.
The E Channel logic version used three card slots (probably in their
entirety) and the drivers used parts of four other cards slots

What to do?  As readers will likely know, you can't do any real logic
with just inverters.  However, SMS card outputs can be hooked together
with all but one of the gates so connected (or "DOT-ed") having open
collector outputs.  Electrically, given the circuits on the DGR and DFS
cards (as well as most others the IBM 1410 uses), if you follow that
with an inverter you get OR => NOT, aka "NOR" logic.  Now that we can do
something with.

So, I wrote a VHDL test bench, based on the Intermediate Logic Diagram
(ILD) that shows the necessary logic for the E Channel (and indicates
the F Channel is the same), and tested that against the E Channel page
to make sure my understanding of the logic was correct.

Then, as an exercise, with liberal application of DeMorgan's theorems, I
proceeded to lay out the logic for the F channel version in that
fashion.  It took 21 inverters (using the AEK as an inverter) and 1 load
resistor (which I probably didn't need to use) and eight DOT functions
(ORs) to produce the necessary logic.  So, pretty close, but not a
perfect reproduction.  One thing is an issue for sure: I "DOT-ed" two
inputs together that come from other sheets whose outputs are used on
still other sheets - which is generally a no-no.  It would not have been
that way on the original machine - they would need to be isolated by
being fed into gates of some sort - even if only back to back inverters.

I could probably spend a bit more time, find a way to leverage the
second input on the gate AEK, and get it more exact, but frankly, it
isn't worth the effort right now.

JRJ