LISP implementations on small machines

[Phil Budne]

Noel wrote:
> The PDP-6 and KA10 (basically a re-implementation of the PDP-6 architecture)
> both had cheapo versions where addresses 0-15 were in main memory, but also
> had an option for real registers, e.g. in the PDP-6: "The Type 162 Fast
> Memory Module contains 16 words with a 0.4 usecond cycle." The KA10 has
> a similar "fast memory option".

http://www.bitsavers.org/www.computer.museum.uq.edu.au/pdf/DEC-10-HMAA-D%20PDP-10%20KA10%20Central%20Processor%20Maintenance%20Manual%20Volume%20I.pdf
p 1-1 (pdf pg 13) says the CPU options were:

KE10  Extended Order Code (byte instructions)
KT10  Memory Protection and Relocation
KT10A Double Memory Protection and Relocation
KM10  Fast Registers

Elsewhere I have the note the the fast registers had 0.21 microsecond
access time.