System/36 Twin-Ax decode help

[alan at alanlee.org]

All, 

I've recently scratched a curiosity itch on what it would take to build
a multi-port Twin-Ax to WiFi bridge.  The electrical interface is easy
enough and ESP32s are cheap.  So I built a bridge PCB-to-FPGA adapter
and connected my System/36 (5362), an InfoWindow II (address 0 and 1),
and my board during IPL and sign-on to see what I could sniff.  The
result is here: 

https://www.retrotronics.org/tmp/s36_ipl_twinax_decode_30nov19.zip 

I get occasional decode errors called out with 'BAD FRAME'.  The [SPF]
next to bytes mean bad start bit (0), parity error, or non-zero fill
bytes respectively.  And I occasionally get a sync pattern followed by
either illegal Manchester transitions or return to idle without any
bytes (and thus no address) - the zero frames in the log. 

My main question is I need help on the next step.  For a brief moment, I
was under the impression SNA LU6 or LU7 ran on top of the Twin-Ax line
layer.  But that doesn't appear to be the case.  I'm not sure it's
direct 5250 either.  Can anyone familiar with IBM-Midrange-World take a
look at the decode and point me to the next protocol layer up the stack?
 Even the slightest breadcrumbs would be appreciated as I know very
little about the Midrange world. 

Additionally if anyone is familiar with the wire-level and could assist
on some of the framing errors, that would help as well.  The twin-ax
cables are less than 2m each so the line should be 100% clean.  The
problems are likely something I am doing wrong in the interpreter. 

Thanks, 

-Alan Hightower