M7264 Troubleshooting

[Mister PDP]

>  Can you check that BHALT on the QBUS is actually asserted (i.e. 0V)
when the switch is in HALT?

I checked the BHALT signal going into the backplane, and it seems to be in
good working order. I took a picture of the readouts for SRUN, which you
can see here:
https://photos.google.com/share/AF1QipOLFAH-Uip-O3LzqZKZVndV2LpGMdNjs4ndyhsKR6aZqqmXD9utlAdkReqoTJyU4A?key=RjExZHdDNC1XTUpkWFhEdU8xLW9vdXBMa2pzY1J3

Checking the BSYNC, it looks like there is life. It oscillates at 58.605
KHz, and has wider peaks than the SRUN signal. This signal does not respond
to the Run/Halt switch being toggled, but I would assume that to be normal
as I have the board jumpered to run at ODT.
https://photos.google.com/share/AF1QipP3G6vBu30RlZUUR6YL3Zjz_LofyJsT-k8TOSYO8ldMhkryuxSdLJ11cq0E9OWBag?key=RlF6R1lTM0ZQc2tMTmN0TnNmdlpzYnM1X1huODFn


On Mon, May 20, 2019 at 11:51 AM Noel Chiappa via cctalk <
cctalk at classiccmp.org> wrote:

>     > From: Mister PDP
>
>
>     > After a day of confusing and mixed up signals (I don't really use
>     > this type of equipment very often) .. I switched over to the
>     > oscilloscope
>
> Don't feel bad, I too prefer to rely on an oscilloscope by default; not
> only does it let you see what's really happening (intermediate voltages,
> noise, etc) but it's simpler, and there are less ways to get incorrent
> info.
>
>     > to confirm that the four clock signals on the MCP-1600 chipset were
>     > working properly .. and was able to see that the very basics of the
>     > CPU were working.
>
> It's not necessarily good if the 4 clocks (I take it that's what the
> latter refers to) are working, because if one or more of those were broken,
> it's a relatively easy/simple fix, whereas if they are working, and
> the CPU's still not running, it could be a failed CPU chip, and the only
> fix there is to replace it.
>
>     > the SRUN signal coming off of the backplane.
>
> Note that SRUN isn't crucial to the machine's operation, it's just user
> info. If SRUN is somehow broken on it's own (i.e. failed component
> somewhere between where the CPU generates it, and the display LED) finding
> and fixing that issue won't help.
>
> Far more useful, in terms of getting the thing running, would be to know
> if BSYNC on the QBUS is hopping around (as ODT tries to talk to the
> console - an easy thing to check into, too). If not, that's a show-stopper
> that needs to be looked into.
>
>
>     > From: Glen Slick
>
>     > the SRUN L signal is driven on to the backplane bus line AF1.
>
> The '78-'78 "microcomputer processors" says (pg. 3-15) that on the LSI-11
> it's also on CH1; just to complete the complexity, it also says (pg. 3-32)
> that on the LSI-11/2 it's also on AH1!
>
>
>     > From: Mister PDP
>
>     > I hooked the oscilloscope up to SRUN off of E68, and found that it
>     > oscillates low at 58.68KHz. .. Hitting the Run/Halt switch does not
>     > have any effect on the period or amplitude of the oscillation.
>
> So maybe the CPU is actually running after all? Although turning
> RUN/HALT to 'HALT' should stop it - the Run light would I think go
> out when ODT is running. (It certainly does on the /23.)
>
> Can you check that BHALT on the QBUS is actually asserted (i.e. 0V)
> when the switch is in HALT?
>
>         Noel
>