Pioneers of computing

[Chuck Guzis]

On 3/12/19 5:59 PM, ben via cctalk wrote:

> That needed to say Half Word. The point I was making was you went
> down from 36 bits to 32 bits and that loss of word size made
> everything follow a similar architecture model between different
> computer manufactures as there is only a few ways to format your
> opcodes to fit into half a word. A bit here, a bit there and WOW you
> need a bigger opcode space. Ben.

It depends on how you design your instruction set.   On the CDC 6000
series, most instructions were 15 bits (6 bits of opcode + 3 x 3 bits of
registers--a 3-address architecture).  Longer instructions were 30 bits.
 Because addresses were of 60-bit word granularity, instruction
placement within a 15-bit parcel was important, as you couldn't just to
a quarter-word address.  I'd programmed S/360 before the CDC machines
and soon learned that there wasn't a whole lot to be gained with byte
addressability.  CDC 6600 COBOL ran faster than the COBOL on a 360/195
(as measured by the Navy Audit Test suite) in spite of the fact that the
6600 has no decimal instructions and is word-addressable--such is the
power of RISC.

--Chuck