Anyone have any info on the obscure MX11 PDP-11 option?

[Noel Chiappa]

While I asking on the TUHS list about the KS11, someone mentioned the MX11
Memory Extension Option, described as "enabl[ing] the usage of 128 KW memory
(18-bit addressing range) ... developed by the Digital CSS (Computer Special
Systems)".

I'm not familiar with this, and I couldn't find anything about it. (It's not
even in the Spare Modules Handbook, but then again, neither is the KS11 -
although the KT11-B is). Some early UNIBUS device address lists (e.g. the '72
"peripherals and interfacing handbook") list up to six, from #1 at 777600-06
to #6 at 777650-56.

I can _guess_ what it did, from the description above (e.g. maps an 8KB block,
since there can be up to 6), but I was wondering if anyone had any hard data;
e.g. memories based on using one BITD, etc, etc.

Even a high level description (e.g. 'sat on the UNIBUS between the CPU and
extra memory, and mapped a fixed block of low UNIBUS address space to a block
controlled by a register') would be an improvement on what we have now, which
is basically nothing.

       Noel