One of the deeper dives into RISC vs CISC I've seen

[Chuck Guzis]

On 6/12/19 10:14 AM, Paul Koning via cctalk wrote:
> 
> 
>> On Jun 12, 2019, at 11:59 AM, Liam Proven via cctalk <cctalk at classiccmp.org> wrote:
>>
>> Goes a bit over my head but may be of interest:
>>
>> https://userpages.umbc.edu/~vijay/mashey.on.risc.html
> 
> Nice.  Still reading through it.
> 
> I like his definition of RISC.  It captures the key points.  Interesting that a substantial fraction of those criteria apply to the CDC 6000 architecture, which some of us like to call out as the first RISC architecture.  Sure, it has only 3 x 8 registers, but when registers are built up out of discrete transistors that's understandable.  The performance considerations that drive the RISC design approaches carry over quite nicely.

There are fuzzy areas.   Consider the ETA 10--a very RISC scalar unit
that pretty much fulfills the criteria laid out, bolted onto a vector
unit (all memory-memory).

--Chuck