Strange third party board in PDP-11/45

[Paul Birkel]

-----Original Message-----
From: cctalk [mailto:cctalk-bounces at classiccmp.org] On Behalf Of Noel
Chiappa via cctalk
Sent: Sunday, July 22, 2018 2:07 PM
To: cctalk at classiccmp.org
Cc: jnc at mercury.lcs.mit.edu
Subject: Re: Strange third party board in PDP-11/45

- MS11-B Engineering Drawings

About all we're missing are the MS11-A/C data board engineering drawings.
(The control board is in the MS11-B prints.)

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Note that the schematics clearly show that the memory controller has direct
access to both the Fastbus and Unibus B, and thus slot 21 (and 16) is wired
for the purpose.

So why have OTT cables to both slots 26 /27 AB?

Perhaps the narrow cable goes to slot 27 to pick up some additional Unibus B
signals, and the wider cable to slot 26 to pick up a larger set of Unibus A
signals equivalent to those to which it already has direct access for Unibus
B).. 

Is this the way that those OTT cables are wired Mattis?

>From the ABLE marketing literature:

CACHE/ 45 (CACHE BUFFER MEMORY) INSTALLS IN: PDP-11/45, -11/50 and -11/55
CAPACITY: 2048 byte (1 K word).
ENHANCEMENT FACTOR: Run time reductions to 50% (100% speed improvement) are
achievable.
CACHE PARITY: Automatically goes off-line in event of any data error.
RANGE SELECTION: User may optimize hit ratio by upper/lower limit switch
settings.
SPECIAL FEATURE: Cache/ 45 can be enabled via software or console switches.

Presumably that's what Mattis has in-hand.

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