Another DCJ11 oddity

[Noel Chiappa]

    > From: Jerry Weiss

    > See http://simh.trailing-edge.com/semi/j11.html for information on the
    > design of the J11.

Thanks for that pointer; I don't think I've ever seen that - quite
interesting.

Alas, it didn't have the cache info - but now that I've though about it
overnight, I'm pretty sure the reason for the two bits that do the same thing
is for -11/70 compatability.

    > I've always assumed the differences in controls in the CCR as necessary
    > to support diagnostics of memory and the cache itself.

Yes, the DCJ11 cache is quite interesting, the way the functionality is
partitioned between the chip itself, and external circuitry; the actual cache
data is stored externally, along with the tags, parity, etc, and also the CPU
and DMA comparators.

The KDB11-A and -B differ a bit in their cache; both are single-associative
(i.e. only one cache cell for each word), but the -B has duplicate tag arrays,
one for the CPU's use, one for DMA devices - apparently so that contention
between the two for access to the tags doesn't slow things down (since the tag
stores are memory arrays, they need to do an address-input before any tag can
be checked).

    > In addition to above, there is a bypass cache bit in the PDR (section
    > 1.5.6.2) for finer control.

Yes, I only found that out last night (or maybe I saw it on a previous scan
of the manual, but its importance didn't register). The -11/70 doesn't have
that! Very useful for my application (a memory tester program)...

	Noel