Core memory emulator using non volatile ram.

[Paul Koning]

> On Dec 15, 2018, at 1:55 PM, Chuck Guzis via cctalk <cctalk at classiccmp.org> wrote:
> 
> On 12/15/18 10:01 AM, Guy Sotomayor Jr via cctalk wrote:
>> FRAM or MRAM.  I make extensive use of them in my projects.
>> 
>> Everspin has a few (all SMT and 3.3v).  As I recall they run ~$20/ea for 4Mb (512K x 8 or 256K x 16).
> 
> As neither MRAM nor FRAM requires a write-after-read refresh, I fail to
> see the "realism" in this that couldn't be satisfied with simple
> battery-backed RAM or even flash-backed RAM.
> 
> Yes, MRAM is magnetic, but ti's not the same principle as real core.

The key question is what the level of accuracy of the emulation is.

If you simply want non-volatile memory, the obvious answer is SRAM with battery backup and a small FPGA to do the interfacing.

If you need to emulate the destructive read, the same but with a slightly more complex FPGA. 

It's hard to see -- other than "because you can" -- why it's useful to emulate the destructive read.  Read/modify/write will work without the destructive read, so long as a write simply overwrites what was in the word.  The only place I can think of where the destructive read propery is useful is in CDC 6000 series peripheral processor memory, at least when you're debugging PP programs that get stuck -- a memory dump taken after a restart will show a zero at the point of the hang.

	paul