Core memory emulator using non volatile ram.

[Warner Losh]

On Sat, Dec 15, 2018, 2:25 PM Guy Sotomayor Jr <ggs at shiresoft.com wrote:

>
> > On Dec 15, 2018, at 1:18 PM, Warner Losh via cctalk <
> cctalk at classiccmp.org> wrote:
> >
> > On Sat, Dec 15, 2018, 1:51 PM Jon Elson via cctalk <
> cctalk at classiccmp.org
> > wrote:
> >
> >> On 12/15/2018 02:45 PM, Anders Nelson via cctalk wrote:
> >>> Serial flash has an endurance between 10K-100K writes per cell so I
> think
> >>> that would break down quickly. Wear-leveling on a serial device would
> be
> >>> very slow...
> >>>
> >>>
> >> If you intend to use it as main core memory on an old CPU,
> >> it will perform VERY poorly, as these memories need to erase
> >> a page at a time, and the erase takes milliseconds.  So,
> >> writing ONE SINGLE word at a time would invoke an erase
> >> cycle each time, slowing it to 1/1000 or worse the speed of
> >> the original core memory.  Also, most old CPUs have the
> >> memory timing built into the CPU, and can't handle a memory
> >> that says "wait".
> >>
> >
> > If you paired it with a microcontroller, you might be able to implement a
> > log device and then manage to logical to physical translation ala FTLs in
> > SSD land... but it would be ugly as heck and you'd still have the stall
> to
> > worry about when you got to the end of the erase block... better
> > performance, but maybe beyond a cheap uc…
>
> And my question is why go through all of that pain when an FRAM or MRAM
> device can do this with no hackery?
>
> What you’re describing is the very definition of an “impedance mismatch”.
> You’re trying to use a block oriented device as a byte device and
> attempting
> to paper over the differences.  I think the end result would be less than
> satisfactory in almost every measurable dimension.
>

True. Lessening the pain still doesn't make it right :). MRAM or FRAM does
sound a lot simpler to use...

Warner

>