Which Dec Emulation is the MOST useful and Versatile?
ben
bfranchuk at jetnet.ab.ca
Fri Oct 27 13:46:34 CDT 2017
On 10/27/2017 9:27 AM, Jay Jaeger via cctech wrote:
> With respect to your #5, I have some direct experience with that, and am
> working on a tricky project to implement the IBM 1410 in a FPGA at the
> gate level, based on the SMS Automated Logic Diagrams (ALD's). What I
> have found so far is that a rule or two can be used to deal with the
> speed and design technology differences. I don't think that the issues
> pointed out make it "hard", really. The hard part, to me, is
> deciphering the original design from drawings or other incomplete
> engineering information. ;) The rules I have developed so far:
>
> a. If the original implementation uses cross-connected gates (or
> transistors), the FPGA model can follow those with a synchronous D
> flip flop. It usually works because the clock times are often 10
> or more times faster or more than the original machine clock. I
> have successfully used this technique to implement an original
> design that was not all that great (see "b." below for details) that
> actually had some race conditions in the original design.
>
> The information on this project can be found at:
>
> https://drive.google.com/open?id=0B2v4WRwISEQRcFpNM0o2VDJiWFk
>
> b. I did not come across delays in the one project I completed
> this way (a re-implementation of a design done for a class in
> college in 1973), but my next project will, and my plan is to use a
> counter (or, I suppose, a small number of cascaded D flip flops
> acting as a bucket brigade) in cases where that delay is needed for
> the implementation to work properly. (In cases where the delay
> exists only to match propagation times along different wire/cable
> lengths in the original implementation, one might be able to turn
> the delay into a wire).
>
> JRJ
With some FPGA venders you could get a TTL library components,
so you could input older designs. You may have to dig around for them
because that is not a NEW selling feature any more. Also logic
cells don't have asynchronous set and clear anymore.
Ben.
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