Kryoflux or Catweasle

[ben]

On 5/25/2017 9:39 AM, Paul Koning wrote:
> 
>> On May 25, 2017, at 11:35 AM, Jon Elson via cctalk <cctalk at classiccmp.org> wrote:
>>
>> On 05/24/2017 02:58 PM, ben via cctalk wrote:
>>>
>>> I am not to sure about that.
>>> If a schematic has a bug you can use a logic probe to find the error.
>>> With typo in VHDL you have hard problem finding that single gate
>>> error.
>>>
>> With Xilinx, they have a VERY good simulator.  You create a "test bench" in VHDL or other HDL to describe external signals.
> 
> You can do the same with other VHDL processors.  If you don't want to deal with a particular manufacturer and potentially pay major money for the tool set, there's GHDL, a open source GCC-based VHDL modeler.  It has some handy capabilities, such as a way to hook C functions into the model.
> 
> 	paul

I use the other BRANDS. I never liked VHDL because I can never figure 
how the logic port mapping works and the on edge logic.
Also what is wrong with custom designs IN ADL,PAL and WINCUPL. Your FPGA
logic is so custom you have no good portable logic for ram or rom on 
chip any how.
Ben.
simulating ttl computer with software.
Simulating ttl with 22v10's.
Simulating 22v10's with FPGA.
easy design and testing.