Kryoflux or Catweasle

[Jon Elson]

On 05/24/2017 02:58 PM, ben via cctalk wrote:
>
> I am not to sure about that.
> If a schematic has a bug you can use a logic probe to find 
> the error.
> With typo in VHDL you have hard problem finding that 
> single gate
> error.
>
With Xilinx, they have a VERY good simulator.  You create a 
"test bench" in VHDL or other HDL to describe external 
signals.  Then, you can probe around like a logic analyzer, 
looking at internal signals behavior, making sure all the 
counters are in the right state, and logic is responding to 
external events, etc.  If that doesn't make it all work 
right, they have ChipScope, which builds a logic analyzer in 
available remaining available hardware on the FPGA, and you 
access it from JTAG.  You compile into your FPGA the points 
you need to see, and then get very similar traces to the 
sim, but it is viewing the signals embedded into the actual 
hardware of whatever you are working on.  If you didn't set 
it up to see the right signals, you change what is included 
in ChipScope and re-synthesize.  It isn't quite as 
convenient as the sim, but it will allow you to figure out 
if some small section of your FPGA is not functioning right 
within a larger system.

With VHDL, you generally do NOT work at the gate level.

Jon