What's the rarest or most unusual computer-related item do you own?

[Glen Slick]

On Fri, Jan 13, 2017 at 4:42 PM, Antonio Carlini <a.carlini at ntlworld.com> wrote:
>
> I'm reasonably sure that the uVAX II did not have a memory cache. It did
> have a translation lookaside buffer and some (small) amount
> of instruction pre-fetch though.
>

Digital Technical Journal, Number 2 March 1986
http://www.dtjcd.vmsresource.org.uk/pdfs/dtj_v01-02_mar1986.pdf

The MicroVAX 78032 Chip, A 32-Bit Microprocessor

All existing VAX processors implement memory
management with a large address translation
cache (at least 128 entries), with system
and process addresses in separate halves. A
translation cache must have a high hit rate to be
effective. Since most caches are direct mapped,
many entries are required to achieve a high
cache rate. Implementing a comparable number
of translation cache entries in the 78032
was out of the question, due to die size constraints.
However, the VLSI technology in the
78032 is very amenable to using a fully associative
translation cache with least-recently-used
(LRU) replacement.

Such a cache needs many fewer entries to
achieve the same hit rate as the direct-mapped
version. In addition, the tight coupling to local
memory, as explained in the next paragraph,
made it possible to reduce drastically the
amount of time required to process a translation
cache miss. Thus the translation cache in
the chip has only eight entries, but the cache is
fully associative, uses true LRU replacement,
and is supported by highly optimized
microcode for fast processing of misses. Moreover,
simulation studies showed that the best
use of the eight entries was with a homogeneous
structure. Therefore, the system and process
addresses are cached together.

The team also decided to forgo the use of an
external memory cache, which required a complex
external interface. Use of an internal memory
cache had already been ruled out due to die
size constraints. Accordingly, the speed of
memory access is 400 ns, or two microcycles,
which is the speed of local memory. Thus the
chip encounters no wait states, and its average
time to access memory is approximately the
same as the 11/780's. In a typical program,
there is little difference between the integer
instruction performance of the two CPUs.