DEC bus transceivers (was Re: Unibus disk controller with modern storage)

[David Bridgham]

On 10/22/2016 12:44 PM, shadoooo wrote:

> What kind of bus transceivers did you used for the QSIC, specially
> because you have
> to go from 5V open-drain logic to 3.3V logic?

To add to Noel's answer, here's a picture of our current prototype board.

http://pdp10.froghouse.org/qsic/qsic-wirewrap.jpg

Coming up from the QBUS, the first two rows of chips are the bus
transceivers.  The next row and a half are the level-converters.  Then
the two large ribbon cables run off to the FPGA module we're using for
development.  The two small ribbon cables go to the indicator panel. 
Just the bus interface takes over half the area of a dual-height board! 
I've played around with laying out what might be the production board
(when I get tired of Verilog and want a mindless break, I doodle with
kicad) and I've got it down to a row of 8641 bus transceivers and a row
or two of the level-converter chips.  It's better but still a good
fraction of the entire board.

http://pdp10.froghouse.org/qsic/proto-pcb.jpg

Now I thought, what if my idea of that two MOSFET bus transceiver would
work?  What would the board look like then?

http://pdp10.froghouse.org/qsic/qsic-smt.jpg

Obviously that could be squeezed down a lot more.  Even another
transistor or two per bus line would still be fairly small.  Doing the
bus transceiver and level-conversion in one step makes a big difference.

For the QSIC, we're going to have sufficient room and we're able to find
enough old bus transceivers to continue on as we're going.  Still, I'd
sure love to have an option that used production parts and took up less
board space.