Reproduction micros

[ben]

On 7/19/2016 9:04 AM, Peter Corlett wrote:
> On Tue, Jul 19, 2016 at 03:30:19PM +0200, Liam Proven wrote: [...]
>> There's a hint here, though:
>> https://www.epo.org/learning-events/european-inventor/finalists/2013/wilson/feature.html
>
>>  From there, it seems to be saying that the essence of the
>> invention is that the
> ARM ISA is RISC, it is a load-store architecture, and the CPU was
> pipelined.
>
> RISC implies a load-store architecture, so that claim is redundant.
>
> Pipelining is an older idea: the 1979-vintage 68000 does it, and the
> 1982-vintage 68010 even detects certain string/loop instructions in
> its pipeline and avoids re-fetching them from memory when repeating
> the sequence.
>
> IMO, it's the predicated instructions that is ARM's special sauce and
> the real innovation that gives it a performance boost. Without those,
> it'd be just a 32 bit wide 6502 knockoff.

And I go the other way, no CPU speed up was really was needed back then.
Cpu's bigger than 8 bits could have decoded and executed the 1st 
instruction, with empty bus cycle then for video or dma or dynamic ram 
refresh.
As for any RISC the 32 bit fetch and the ability
to cache effective addresses makes its speed.
Ben.
PS: With the amount cache to today's cpu's, would a delay line computer
be a better working model, than that of Random Access Memory?