UNIBUS/QBUS interface chips Was: Re: MEM11 update

allison ajp166 at verizon.net
Tue Dec 6 13:24:21 CST 2016

On 12/6/16 10:05 AM, Toby Thain wrote:
> On 2016-12-06 1:34 AM, Eric Smith wrote:
>> On Mon, Dec 5, 2016 at 6:53 PM, allison <ajp166 at verizon.net> wrote:
>>> A bunch of us old digits (former dec engineers) got together and were
>>> talking
>>> about old systems and the thing that stood out is a general dislike for
>>> having
>>> to use the limited set of bus interface chips when there were newer
>>> parts.  It
>>> was a internal mandate not something that was better than could be had.
>>> The
>>> logic was the parts were known, the vendors vetted for quality and
>>> reliability
>>> and when you use hundreds of thousands to millions of a part like bus
>>> interface
>>> and ram quality is a critical thing.  Were they special, a flat no.
>> I don't fully agree. The receivers (and transceivers) had a threshold
>> voltage that is not available with modern parts, and that actually was
> I'm an electronics noob, but do you mean a threshold of 1.5V, as with 
> DS8641?
I'm not a noob.  I'm an engineer from the the realm of DEC engineering.

I also forget the 74LS14 hex inverter with hysteresis which has a 
threshold about 1.5V
depending on whos datasheet you believe.

Bottom line is the older parts has a low Vih and a high Vil with a 
resulting narrow noise immunity.
Increasing the Vih helps this and the driver/bus combo can support it.  
The yabut is if the drivers
have leakage then attaining Vih on the bus is problematic as the leakage 
was a undesired pull down.
The 8xxx parts used were screened for low leakage with output is in the 
high state (open as they
are open collector).  The bus loads assert the Voltage high state and 
that is above 2.3V so the only
limiting factor then is excessive capacitive loading which smears pulsed 
by RC time constant.  The
other issue with slow edges is where the edge really is and that adds 
uncertainty to timing.   All
of those things were allowed for in the design of the bus.

The voltage your hung up about was  tested to insure it was never lower 
than that or the noise
immunity was terrible.  Its companion was was that the saturated device 
in the package could
also achieve the limit or less or a low voltage at the rated current, at 
that time (late 60s early 70s)
this was a hard parameter to control.

The bottom lime is the better the logic high voltage and logic low 
voltages achieved the greater
noise immunity.  Adding hysteresis insure that a hig is high and a low 
is low and not some random
analog voltage inbetween (or oscillation!).

As to any slew rate testing the issue was that devices that could sink 
the needed current were also
slow as sludge and had to be tested to insure they were fast enough not 
that they would have a
slow propagation time and switching speed as that was also a undesired 
in systems where fast
is important.  Bottom line is the datasheet and purchase spec was to 
insure the part worked to or
better than expected rather than implying magical properties.


> I'm referring to this part of October's thread:
> http://www.classiccmp.org/pipermail/cctalk/2016-October/028871.html
> --Toby
>> important for large systems with multiple bus segments.  That was
>> particularly important for large Unibus systems, but even Qbus with only
>> two bus segments can get finicky when heavily loaded.
>> DEC could easily have made custom interface ICs if they had needed them.
>> AFAIK, *no* current production interface ICs have the right 
>> threshold. It's
>> hard to meet the spec without using either NOS parts or comparators.
>> It would certainly be possible to build a functionally equivalent bus 
>> with
>> modern interface ICs, and it might have significantly better 
>> performance,
>> but it wouldn't be compatible with the legacy systems.

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