AlphaStation 200 NVRAM Problem

[Maciej W. Rozycki]

On Sat, 23 Apr 2016, Robert Jarratt wrote:

> >  That's a bit cryptic, but knowing that this is a low-level CPU interface
> you can
> > gather the wiring from this document:
> > <http://h18000.www1.hp.com/cpq-
> > alphaserver/technology/literature/164lxtrm.pdf>.
> > So BSROMCLK is Tx and SROMCDAT is Rx, but as noted here and in the
> > discussion in the first reference you need an EIA/TIA 232 driver and
> receiver
> > (there is power available on the diagnostic port, so you can use it for
> the
> > circuit), and of course you need to cross the lines wiring them to your
> host.
> > 
> 
> I don't think the SROM diagnostics are going to help much because the
> failure is in the DROM sequence, which comes after the SROM.

 But from the discussion referred I gather DROM outputs its diagnostics to 
this port too and you might be able to learn what exactly about NVRAM it 
complains.  Also you might be able to correct configuration, e.g. by 
poking at NVRAM or elsewhere appropriately; notice that the manual also 
suggests you might be able to bypass the DROM sequence and go to SRM/ARC 
directly, which might help recovery too.

 It's up to you if you want to try this of course, I just thought it might 
help as the existence of this SROM console might not be universally known.

> >  Finally the SROM console command reference is here:
> > <http://h18000.www1.hp.com/cpq-
> > alphaserver/technology/literature/srommini.pdf>.
> > This manual doesn't specifically cover the Avanti, but I'd expect the user
> > interface to be similar -- it's a low-level tool close to the CPU after
> all.
> > 
> >  NB on Avanti the 8kB NVRAM is separate from the TOY/NVR chip (which is a
> > Benchmarq BQ4285, providing 114B of general storage only).
> > 
> 
> I had already located the Benchmarq chip and found the spec to be
> insufficient for the 8K NVRAM. The problem is, I don't know which chip has
> the NVRAM, I have not been able to locate it and the manuals don't tell me.
> I hope it isn't one of the ASICs. I have posted a photo of the board here:
> http://bit.ly/1qHQnaB in case anyone can id the NVRAM.

 It is separately decoded on the flashbus (among flashROM, DROM, 
diagnostic LEDs and jumpers), so I doubt it's in an ASIC, that would be 
too arcane.  I suspect they wanted to keep it separate from flashROM for 
safety.

> If the NVRAM contents are maintained by the battery then there should be a
> way to reset the NVRAM contents, but there does not seem to be a way. I
> wonder if the NVRAM persists without power? The manual seems to say that the
> TOY is battery backed, but makes no mention of the NVRAM needing the
> battery.

 It is battery backed indeed and it sits right in the upper right hand 
corner: <http://web.mit.edu/6.111/www/s2007/datasheets/KM6264B.pdf>, next 
to the other flashbus devices, as expected -- next to the left there is a 
pair of flashROMs (and a pair of sockets for another two of the four 
supported total), and a socketed DROM chip.  Being decoded as a DRAM bank 
they are also close to DRAM sockets.  Jumpers and LEDs are elsewhere, but 
obviously they have less strict PCB routing requirements.

 HTH,

  Maciej