WD9000 Pascal microengine schematics available

[Eric Smith]

On Tue, Nov 10, 2015 at 1:39 PM, Brad Parker <brad at heeltoe.com> wrote:
> Don't you also need to "delayer" the chip to get all the hidden features?
> I thought the process of reconstructing the polygons required that each
> successive layer be exposed.  From the "top" I'd think you'd only see a
> single metal layer.  But then again, on a old chip like that there may only
> *be* one metal layer :-)

For late 1970s coarse geometry NMOS with only one metal layer, it's
usually possible with only a single photomicrograph, especially if
there isn't a thick passivation layer. That's how the 6502 was
originally reverse-engineered. As the processes became more complex
and added more metal layers, reverse-engineering has increasingly
required delayering.

The use of depletion mode nFETs for loads does make it a little more
difficult, as you can't see the difference in the diffusion, but it's
usually possible to infer which nFETs are the loads.

The LSI-11, WD16, and WD9000 chipsets are three-supply-voltage NMOS,
so they shouldn't even have any depletion loads to worry about.
Depletion-load NMOS eliminated the +12V requirement, so was usually
only used for single-supply 5V parts, Mostek pioneered depletion-load,
and one of the earliest commercial uses was the Zilog Z80 CPU, which
was originally fabbed by Mostek both under contract to Zilog and as
Mostek's second-source.

Usually along with depletion-load, an on-chip substrate bias generator
eliminates the Vbb requirement, which was usually -5V.