8257 use in Intel MDS IOC

Eric Smith spacewar at gmail.com
Mon May 4 03:43:11 CDT 2015

F.Ulivi wrote:
> My understanding is that an hw
> modification is needed to IOC board if 8237 is installed (see for
> example the wiring around the DMA in this picture:
> https://www.flickr.com/photos/22368471@N04/16932740579/in/album-72157651893890975/
> ). This rewiring (for which I found no documentation) apparently allows
> the 8237 to "emulate" the autoload feature of 8257.

That's actually my IOC board. I hadn't noticed that it has an 8237A!
Amazing. Thanks for pointing that out.  That's definitely proof that
the code can work with the 8237A, now I need to scrounge an 8257 and
determine whether the board w/ the 8237A rework will still work with
the 8257.

IIRC, the 8237A had some improvements over AMD's original 8237 design,
so it's possible that a non-A 8237 might not work. I haven't compared
the A and non-A datasheets yet.

I've been making progress on reverse-engineering the IOC firmware.
They wrote it as four separate 2K ROMs, each of which has a table of
fixed entry point addresses for entry from the other ROMs. (The first
ROM has the entry points interleaved with the RST n vectors.)  The
first ROM is startup and diagnostics, and the second is the command
handler and the driver for the intergral single-density floppy.  I
haven't yet started on the third and fourth.  There are a few input
and output bits they access that are not used in the normal IOC, but
perhaps are used in the IOC-III used in later Series III machines.

In the RAM test, if the back panel mode switch is set to diagnostic
mode, they insert a delay (which I haven't timed) between the write
and verify passes of the diagnostic, presumably to test whether memory
refresh is working.

I was hoping that the floppy driver had support for two drives, but as
far as I can tell so far, it does not. I could be wrong since I
haven't puzzled out all of the details yet.

My IPB is the old version (1001194) without the 20-bit addressing
daughterboard (1002234). I don't have a schematic of the daugherboard,
but all it does is use a 74LS30 and a resistor pack to pull up the
A10/ through A13/ address lines on the Multibus, and disable the
on-board RAM address decode if they aren't all high, in order to
prevent the board from incorrectly responding to RAM addresses from
0x10000 through 0x17fff, 0x20000 through 0x27fff, etc.  I can easily
hack that in myself.

I'd really like to replace the IPB with the 8085-based IPC, if anyone
has a spare available. Also looking for an RPA, RPB, or RPC 8086 board
to effectively turn it into a Series III, and the two-board
double-density floppy controller. (This Series II was previously
equipped with the double-density controller, as the I/O cabling is
still present.)

Also it would be nice if anyone has a later rev of the Series III
schematics. The set that Al has kindly provided on Bitsavers is
121642-001A, which appears to be the earliest set Intel printed, and
doesn't cover the RPB or RPC, or the IOC-III.

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