Qbus split I&D?

[John Wilson]

On Tue, Mar 17, 2015 at 05:02:37PM -0400, Noel Chiappa wrote:
>UNIBUS RAM cards? Neato-keeno!! When will they be available, and how do I
>order some? :-)

I think Guy's MEM11 is going to be way cooler.  I made my board in 2012
to scratch my own itch (but then didn't get it running in time and had to
spend real money on an MS11LD after all), and it's a memory-only device so
it plugs into the A/B positions of a MUD/SPC slot, which makes it useless
on an 11/20 which doesn't have those (right?  unless you add a BA11K?),
and can't emulate anything that does DMA or interrupts (but that still
leaves a few things).

I'll be doing a new rev one of these months (to incorporate ECOs and
battery holders and add more devices, now that I did the CRC emulation for
E11 anyway) and then I'll certainly make them available, but not seriously
expecting anyone to order one.  Guy's MEM11 is nicer!

>BTW, what's an 'XMOS'? Google didn't enlighten me...

Sorry -- XMOS is the successor-in-spirit to Inmos.  They make the XS-1
microcontrollers, which are wonderful (eight hyperthreads at 50-100 MIPS
each, with a lousy base instruction set but fantastic event handling and
timers and locks and inter-hyperthread pipes -- in half a dozen projects
I've never needed to use interrupts).  I used it instead of loose logic for
range checking and decoding MSYN/C0/C1 and generating SSYN just because it
was worth the cost savings in PCB sqinches at qty=1, and still way faster
than a real MS11L.  But now that it's there, it makes all kinds of device
emulations easy (TOY clock for starters).  Plus it's jumperless -- it's
perfectly easy to have a hyperthread bit-bang a UART so there's a
DLV11J-style plug for a TTY that does config, and there's already flash in
the RTCC chip (besides what's hanging off the XMOS CPU).  Naturally I've
gotten way sidetracked writing that firmware;  XON/XOFF works, you can
delete tabs w/o messing up the cursor, it figures out the day of the week
if you say "set date 17-Mar-2015", etc.  Totally out of hand.

Speaking of sidetracked, I'm intrigued by the Enable/34 discussion.
I was thinking of making Rev B have 4 MB memory anyway, since it sounds
(from the MS11P manual) as if the 11/24 and 11/44 extended Unibus would
be easy to support as an option (seems like the four extra address bits
on AN1, AP1, BE1, and BE2 are all that's new, and the I/O page still works
normally in the highest 8 KB even though it's mostly a memory-only bus).
But for 18-bit machines, emulating the Enable thingy might be fun for a
tiny handful of people, which is always enough to justify months of work
in my book.  Even if it means adding parts to diddle the address bus.

But thinking about how it must work hurts my head.  It's emulating Unibus
memory at the same time that it's emulating the Unibus map -- i.e. CPU
accesses (which should be relocated through the onboard PARs) are coming
over the same bus as DMA (which should be relocated using the Unibus Map).
How does it know which is which?  Does it need to tap into each model of
CPU somehow (like how a Microverter gets at MMR3)?  Or is it something
simple like, BBSY is never asserted by the CPU (not obvious from docs --
the CPU doesn't need to negotiate to become a master but it still is one
when it's accessing memory) so if it's on, this is DMA?  And what if there's
a cache, like the KK11A, that doesn't know about the outboard PARs?

Anyway here's a picture of Rev A:

	http://www.dbit.com/wilson/uram.jpg

John Wilson
D Bit