Qbus split I&D?

[Johnny Billquist]

On 2015-03-17 20:03, Christian Gauger-Cosgrove wrote:
> On 16 March 2015 at 23:42, Eric Smith <spacewar at gmail.com> wrote:
>> Not including parity or ECC, it takes two devices to fill the entire
>> 4MB address space of the PDP-11/70. Either parity or ECC will require
>> another one additional device, which won't be fully utilized.
>>
>> Ordinary SRAM is cheaper, but $110.16 for enough RAM chips to max out
>> a PDP-11/70 doesn't seem all that expensive, unless you're comparing
>> to DDR SDRAM DIMMs for PCs.
> True, SRAM would be cheaper, and you can find faster SRAM and DRAM
> than the currently available MRAM (if I recall correctly). But then
> you lose the benefits of MRAM in the first place: It's non-volatile,
> like core memory, and doesn't need battery backup (as you'd need if
> you wanted to make SRAM "non-volatile"). Plus since they're modern
> devices, they would be a massive upgrade to the PDP-11/70s performance
> in place of its normal MOS memory or core memory. (Whether it would be
> an improvement on the speed of the PEP70, I do not know.)

You can't improve on the speed of the PIP70/HC70 combo. At that point, 
the speed is just the clock speed of the CPU. It no longer waits on 
memory, as far as I know.

But getting to that point would be a nice improvement already.

	Johnny