Leading NOPs for boot code

[dwight]

 Reading Eric's 432 post, I saw a note about leading NOPs at the start
of boot code.
The 4040 code that 'd seen always did this. While working
at Intel, I'd found out why.
It seems that the reset in their APnote actually released the reset
for the processor before the ROMs.
The NOPs were hoped to give the processor time to get the ROMs
sync'd. The processor would fetch a couple reset states from the bus
before the ROM data would show up. If all worked well,
The first address wouldn't get garbled by the reset release in the
ROMs and it would do its first real operation as a NOP.
This didn't always happen, though. 
By changing the order of the reset releases, reset was much more
reliable. Both would start on the first sync pulse from the 4040.
They did need to be closely timed because of the dynamic nature
of the ROM address registers.
Dwight