Reproducing old machines with newer technology (Re: PDP-12 at the RICM)

[Paul Koning]

> On Jul 14, 2015, at 7:40 PM, Jay Jaeger <cube1 at charter.net> wrote:
> 
> On 7/14/2015 11:27 AM, Paul Koning wrote:
>> ...
> 
>>> 
>>> 3)  Flip flops which are clocked from combinatorial signals.  These tend
>>> to cause timing/glitch issues.  For example, in one case the
>>> combinatorial output was a zero-check on a counter.  Since the counter
>>> flip flops did not all change at exactly the same time, that signal
>>> could glitch during the simulated machines master clock edge.  They
>>> respond well to the same general solution as #1 - stick a D flip flop
>>> between the combinatorial output and the clock input.  In the case I
>>> mentioned, that gave the signal an entire 50 Mhz clock period to settle
>>> down.
>> 
>> That sounds like a bug in the original.  If you have a set of flops clocked by some signal, and it matters that the outputs don’t all change at the same time, then the original wasn’t reliable either.
> 
> That is just it - the combinatorial inputs were used FOR the clock on
> some gates.  Right - not a good idea even back in 1972, though it
> depends a little on what the rejection time / intertial delay of the
> inputs are, but yes - certainly a design that would be prone to failure
> (remember that this was a bunch of students trying to put together a
> working 12 bit computer in about a month - ours included a cross
> assembler and cross-interpreter, so we had real software running our
> machine for its demo - including hangman played with the TTY keyboard
> and an oscilloscope hooked to a pair of D/A converters for a display).

Good points.  So my conclusion is that the best answer depends on the design you’re trying to copy.  If it uses this sort of tricks, or this sort of “well, it worked once” style of design, then you’re going to have a harder time.  If the design is basically sound synchronous logic, as in the case of the 6600 (once you look hard enough) then it’s not such a problem.  Not so long as you avoid oddities like the original clock (serial numbers 1-7 only) which is a ring oscillator of 4 double inverters and 4 well chosen lengths of wire.  But serial numbers 8 and up replace that by a proper crystal clock, so that’s the one I use (substituting the FPGA external clock input for the one on the ECS Controller).

	paul