Problem with DEC LSI11 / KD11-F

[Eric Smith]

On Sun, Nov 30, 2014 at 4:32 AM, Mattis Lind <mattislind at gmail.com> wrote:
> How did you do the dumping?

Supplied power and four-phase 12V MOS clock.

Just after start of phase 1, micro drives address on MIB<10..00>, all
others high.
Just after start of phase 2, micro drives all MIB lines high, waits
briefly, then sets all to Hi-Z.
Just after start of phase 4, read MIB lines.

The missing part is how to dump the PLAs in the control chip. Will
probably have to do that optically.

> The unconditional precharge, conditional
> discharge structure seems quite elaborate. Or maybe it is just to do have a
> OC driver enabled at phase 2?

Unconditional precharge is easy, it always happens at the same time(s)
during the cycle, though MIB<16> and MIB<15> are different than the
others.  However, the Microm doesn't care; it only requires that they
have the address (and /MIB16 high) at the start of phase 2, and then
all precharged high once it's latched the address, so it can use
conditional discharge to drive the outputs.

It's the control and data chips that put more complicated requirements
on precharge, but since they're not present when dumping a Microm,
those requirements aren't either.

Conditional discharge is as you say, just OC drivers.

> Do you have dumps of the micro code?

I had just dumped one Microm, I think successfully but I don't know
with certainty, before I moved 2 1/2 years ago. I haven't found the
bits since, so I may have to do it again.  Not a big deal since I want
to dump other Microms anyhow.

> If dumping is easy (?), now how does this precharge thing work in you
> emulator?

Same as the KUV11, just use the real Microms for precharge.  They'll
do that even if you ground their enable input.

If I really wanted to do precharge in the emulator, I'd add one pFET
with series resistor to each MIB line, and inverters from phase 2 and
phase 4, and a NAND gate from both, to enable the appropriate FETs.