idea for a universal disk interface

[Guy Sotomayor]

I'm using Zynq SOMs (System on a module) that will plug into a "base 
board" (with hilrose connectors).  It is the base board that will have 
the "personality" of the emulator.  The baseboard will be fairly simple 
(level shifters, a small bit of logic and the drive interface 
transceivers).  So the base board is fairly simple (I think I have an 
early version in KiCAD...but it needs updating).

I'm trying to use as much as I can from the free libraries so I'm trying 
to keep stuff as simple as possible from a logic design perspective.  
Since I already have everything (in multiples) except for the base 
board, the cost to me is time at this point (which I don't have a lot of 
at the moment).

I also didn't want to get into doing any design with BGAs (at least 
where I need to worry about it) hence the decision to go with SOMs.  
With those, the SOM has the Zynq FPGA, flash, DRAM, etc (including the 
critical VRs and clocks).  All I need to provide is 3.3v.  ;-)

I should be able to dig up the docs.  Many are already on bitsavers.  
Let me know what you can't find on Bitsavers.

TTFN - Guy

On 4/20/22 11:22, shadoooo via cctech wrote:
> Guy,
> I agree that accessing data in blockram (synchronous with fixed latency) is really easier than accessing it from RAM (asynchronous with variable latency).
> Anyway I'm weighting the "cost" of additional complexity, which in change would allow to spare on Zynq cost.
> In any case memory access is never sequential, but a sequence of bursts with shorter length (16 beats or less).
> Considering this, the fact of starting or ending a sequential transfer is just a matter of generating addresses multiple of burst length. For this however you have to forget about Xilinx's free IP cores, and work directly with AXI3 bus of HP ports.
>
> As I would have to invest a large amount of time and of money, it would be nice to have somebody interested in buying a working and assembled kit with moderate price gain, in way to repay part of the investment.
> This however drives to bottom end FPGAs, with very limited amount of internal memory... whence the memory-spare design.
>
> About documentation: you mentioned several documents about SMD/ESDI standards and related details.
> Would you mind sharing this collection?
>
> Many thanks.
>
> Andrea

-- 
TTFN - Guy