PDP 11/24 - A Step Backwards

[Rob Jarratt]

> -----Original Message-----
> From: cctalk <cctalk-bounces at classiccmp.org> On Behalf Of Rob Jarratt via
> cctalk
> Sent: 02 April 2022 11:58
> To: 'Noel Chiappa' <jnc at mercury.lcs.mit.edu>; 'General Discussion:
On-Topic
> and Off-Topic Posts' <cctalk at classiccmp.org>
> Subject: RE: PDP 11/24 - A Step Backwards
> 
> >
> > Disconnect the bad ACLO, power it on, and see if the CLK LED comes on.
> > if not, then we'll have to work out why not.
> 
> This is my plan for later today.

OK, so I disconnected ACLO only. It was quite a struggle to separate those
nylon connectors, is there a trick to it? In doing so I spotted two
backplane wire wrap pins touching and a couple of others that were quite
close too, so I separated them and inspected all the backplane pins. I
didn't see any other ones touching. When I powered on, the CPU LEDs did not
light up. Some random characters appeared on the console, but probably just
a bit of noise maybe? However, I did notice that the CLK LED flickered on
briefly when I powered it off. I put a scope probe on TP1 (p152 of the PDF),
there was no activity, the pin remained high.

The problem now is that I expect I will need to probe various pins to find
out what is going on. But I don't have a Unibus extender and I am reluctant
to remove the backplane. From what I can tell in the Technical Manual you
can't install the CPU in other slots to make room for attaching probes
either. I am forced to tack solder probe wires to the chips, which works but
is time consuming. Any other ways?

Using tack soldered wires, I have traced back and I *think* I have found
something. There could be a fault in E52 (sheet K6, p157 of the PDF). While
K6 BUS DCLO L is +5V, I am measuring K6 BUF DCLO H at an average 1.64V with
50us spikes at 2.08V. According to a NatSemi datasheet for the DS8641
(http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS005806.PD
F) the logical 0 output should be 0.4V max and the logical 1 output should
be 2.4V min. I also measured K6 BUF DCLO L to be always low, suggesting it
thinks the K6 BUF DCLO H is a logical 1. This seems to suggest that E52 may
be faulty. Trace here:
https://rjarratt.files.wordpress.com/2022/04/e52-dclo-signal.jpg.

Regards

Rob

> 
> >
> > 	Noel