Pipelining and Dec Jupiter thoughts....

[Jon Elson]

On 05/07/2021 07:10 AM, Paul Koning via cctalk wrote:
>
> They built an interesting hybrid system where you could 
> write the design partly as geometries (for things like 
> memory cells), partly as transistors, partly as gates, and 
> partly as C code. I remember an example, where they had a 
> transistor schematic for a single-bit latch, and then 
> wrapped it in a loop: "for (i=0; i < 64; i++) { 
> <schematic> }". The magic was that (apart from the few 
> bits of explicit geometry-level design) it was all 
> parameterized, so they could regenerate the actual wafer 
> geometry overnight for a new fab. 
That sounds a lot like VHDL, which can be used to synthesize 
chip layout.
>  Another part of the puzzle was figuring out how to feed 
> 100 watts of power to a chip, and get rid of that amount 
> of heat, neither of which were anywhere close to what was 
> done at the time. I still have some of the tech reports 
> that describe that piece (and I contributed a wild idea -- 
> which unfortunately DEC didn't get around to patenting 
> before the project was shut down). paul 
IBM was tinkering with high density ECL system construction 
from 1965 or so, as a follow-on to the System 360.  They had 
several aborted projects, FS (Future System) and ACS 
(Advanced Computer System) that were very advanced 
supercomputers.  The technology eventually came out as the
309x series, with several hundred MSI ECL chips on a ceramic 
interconnect substrate, water-cooled
with a big plate with copper "nails" that pressed down on 
the back of the ICs.  That was the 308x system, introduced 
in 1984.

Jon