General Instruments Capacitive Keyboard Encoder

[Tony Duell]

On Wed, May 5, 2021 at 8:12 AM Paul Birkel <pbirkel at gmail.com> wrote:
>
> > -----Original Message-----
> > From: Tony Duell [mailto:ard.p850ug1 at gmail.com]
> >
> > > On Tue, May 4, 2021 at 10:33 AM Paul Birkel via cctalk <cctalk at classiccmp.org> wrote:
> > >
> > > I'm currently reverse-engineering an AMPEX keyboard that uses capacitive key
> > > switches.  The basic design employs a GI encoder coupled to an 8039 MCU
> > > supplemented by a 2K EPROM and 74LS373 (used to latch the ROM address set
> > > from Port A while Port A is then used to read data back from the ROM).  The
> > > 8039 MCU drives a bit-banged serial interface.  ...
> > >
> > > The GI encoder is a DIP-40 labeled as "321239007  M2406-054-02  GI 8233 CBU
> > > TAIWAN".  I seek technical documentation for this IC.
> >
> > You might take a look at the manuals here :
> >
> > http://cpu-ns32k.net/Whitechapel.html
> >
> > I am pretty sure there's a keyboard techincal description in 'binder
> > 1' and a reverse-engineered schematic in 'binder 2'. While it's not
> > quite the same IC, it's related and the power pins are in the right
> > place :-)
> >
> > Alas there is no real description of what that IC does or how to talk
> > to it from the 8039. It is designed to sit on the 8039 bus, it takes
> > in the multiplexed address/data bus, ALE, rd/ and wr/
>
> Bingo.  That's basically my circuit here (pin for pin) with minor differences in RC values and a much more interesting serial interface (and a _four_ finger salute no less!  N-S-T-V  Take that DOS ...), although mine supports a buzzer/speaker.
>
> The principal inconsistency is that pin 25 is marked "CS" and left open in the "binder 1" schematic (page 132 of 134), and then doesn't appear in your hand-drawn schematic (page 7 of 24).  In my circuit it's wired to the 8039 ~PSEN.
>
> The straight-thru wiring on ~RD and ~WR alongside ALE with no address decoding is IMO rather odd.  I wonder how that design actually works (either assumes that it is the only writable device present, or actually latches 8 bits of address and shadows some valid ROM address) and then what gets written to the encoder for what purpos(es). Disassembly of the EPROM should answer those questions.  My objective here is to replace the bit-banged interface with a parallel interface emulating one for an Intel MDS-230.

Remember that the 8039 has separate program and data memory spaces.

PSEN/ (Program Store ENable) is asserted to access the ROM .If pin 25
of the keyboard scanner chip is CS, that might be Chip Select (active
high), to ensure the chip is disabled on ROM accesses.

Rd/ and Wr/ are asserted to access data memory. Here the only device
is the keyboard scanner chip, so there's no need for address decoding.

Since the keyboard scanner chip takes in ALE, there's a chance it uses
the lower 8 address lines (multiplexed with the data bus) to select
different internal registers,
>
> Two questions on notation.:
>
> 1. In the "binder 1" schematic pin 6 is marked as R<sub>y and is pulled up via resistor to +5v.  On your hand-drawn schematic the corresponding pin appears to be labeled "PVR".  What might be the function of this pin?
>
> 2. In the "binder 1" schematic pin 15 is marked as C<sub>m and is attached to an RC circuit.  On your hand-drawn schematic the corresponding pin appears to be labeled "RC".  C = 100 nF.  What might be the function of this pin?  I'm guessing ~(Power On Reset) rather than as the basis for an on-chip oscillator as seen in the AY-3-4592 pin 36 "RC" given the relatively high capacitance value.

My guess is that I called the first 'PUR' for pull-up resistor :-) It
may actually set the sensitivity of the row inputs or somethng.

The second may be an RC delay to allow the keyboard to settle. There's
something similar in the PERQ2 keyboard which uses separate row and
column chips.

-tony