(V)HDL Toolsets

[Tom Uban]

On 5/21/20 9:51 AM, Paul Koning via cctalk wrote:
>
>> On May 20, 2020, at 10:22 PM, Jay Jaeger via cctalk <cctalk at classiccmp.org> wrote:
>>
>> As I wrote in my last post, but write here for use as a separate thread:
>>
>> I'd be interesting in hearing from folks what toolsets they have used
>> for HDL (VHDL in particular).  I started with Xilinx ISE and then
>> graduated to Vivado for later chipsets - unfortunately, Vivado seems to
>> be something of a dog, in terms of time to compile HDL and synthesize logic.
>>
>> JRJ
> I have been working, very slowly, on a project analogous to yours: a gate level model of the CDC 6600 supercomputer. 
>
> The source material for this is the wiring lists, which show the module connections and also the module logic diagrams.  I used the diagrams to create gate-level models for each module, and ran the wire lists through OCR to get the connections.  Those are then run through a simple Python program to generate the equivalent structural model.
>
> I wanted to start with simulation, and treat synthesis as a later step.  So rather than use any particular vendor tools I used GHDL.  That works quite nicely.  Among other benefits, since it generates executable code (it's a GCC front end) it can call C functions.  In my case, the memory and I/O devices are C models, which the VHDL code talks to.  GHDL supports output to GTKwave to let you see what it is doing.  And, at least to some extent, you can use GDB on it.  I haven't done much of that.
>
> The whole process of going from wiring to VHDL is quite straightforward.  Getting the wire lists exactly correct takes some work partly because of OCR errors and partly because there may be typos in the wire lists.  Also in the 6600 case, the wire lists are per chassis and they aren't all the same revision of the product. :-(
>
> If the timing in your machine is reasonably sane and has enough margin, the simulation should be painless and synthesis should produce few issues.  If you have bits that are sensitive to wire or circuit delays, that's different.  Unfortunately, the 6600 is utterly infested with such issues, to the point that it's hard to see how it ever worked at all -- the timing documented in the manuals and implied by the wiring can't actually work.  A 1410 is probably better, especially considering that IBM had some senior designers who had experienced timing pain first-hand and had learned to avoid it.  I'm thinking of people like Gerrit Blaauw (not sure if he was on that project, though).
>
> If you have delay-sensitive elements, that will probably require adding extra stages to the logic, such as additional latches, to produce the required sequencing with modern logic, which in turn may require extra clock phases.  Here too the 6600 is amazingly painful: I found myself with a 20-phase clock to get even close to sane operation, in what is typically described as a four phase clock design.
>
> Others have mentioned Verilog.  I have no experience with that.  I landed on VHDL mostly by accident, because I wanted an open source simulator and GHDL showed up.  There may be open source Verilog simulators at this point, I'm not sure.  Avoiding Windows was also a requirement.
>
> 	paul
>
Paul, your project is super interesting. Is there a website where I can track it?

--tom