DIBOL and RPG for RSTS
Guy Sotomayor
ggs at shiresoft.com
Sun Mar 29 11:13:27 CDT 2020
On Sun, 2020-03-29 at 10:21 -0400, Paul Koning via cctalk wrote:
> > On Mar 28, 2020, at 2:55 PM, dwight via cctalk <
> > cctalk at classiccmp.org> wrote:
> >
> > There are a few reasons most don't like Forth:
> >
> > 1. no type checking ( suppose to save dumb programmers )
> > 2. Often, no floating point. ( Math has to be well thought out
> > but when done right in integer math it has few bugs ).
> > 3. Few libraries ( One can often make code to attach to things
> > like C libraries but it is a pain in the A. Often if you know what
> > needs to be done it is easier and better to write your own low
> > level code. Things like USB are tough to get at the low level
> > stuff, though )
> > 4. To many cryptic symbols ( : , . ! @ ; )
> > 5. To much stack noise ( dup swap rot over )
> >
> > I still use Forth for all my hobby work. It is the easiest language
> > to get something working of any of the languages I've worked with.
> > ...
> > Learning to be effective with Forth has a relatively steep learning
> > curve. You have to understand the compiler and how it deals with
> > your source code. You need to get used to proper comments to handle
> > stack usage. You need to learn how to write short easily test words
> > ( routines ). It is clearly not just a backwards LISP. It is not
> > Python either.
> > Dwight
>
> No, it certainly isn't Python, which is my other major fast-coding
> language.
>
> FORTH started as a small fast real-time control language; its
> inventor worked in an observatory and needed a way to control
> telescopes. It's still used for that today. I recently went looking
> for FORTH processors in FPGA, there are several. One that looked
> very good was designed for robotics and machine vision work. The
> designer posted both the FPGA design and the software, which includes
> a TCP/IP (or UDP/IP ?) stack. He reports that the code is both much
> smaller and faster than compiled C code running on conventional FPGA
> embedded processors.
>
Yes, that would be J1. I've used it and even wrote a simulator for it
(in FORTH 'natch) so that I could debug my code. It's a useful FPGA
implementation.
TTFN - Guy
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