MSV11-Q info and interesting observation

crufta cat ucespamdump at gmail.com
Mon Mar 16 12:37:07 CDT 2020


Yes very common with Dram arrays.

Similar to write enable on Chipselect for Sram arrays.

Allison

On Sat, Mar 14, 2020 at 4:20 PM Chris Zach via cctalk <cctalk at classiccmp.org>
wrote:

> Noel, you're incredible! Thanks for fuzzing this out, I've been working
> on chiming clocks as of late and put this board on the back burner, but
> with this swapping out the bad chip should be a piece of cake.
>
> Thank you again!
> CZ
>
> On 3/14/2020 4:12 PM, Noel Chiappa via cctalk wrote:
> > So, a while back someone had a broken MSV11-Q QBUS memory card, and
> needed
> > info on them. I said I'd provide same, but then got distracted. Well, I
> > finally got to it, and it's been added to the CHW page for them:
> >
> >    https://gunkies.org/wiki/MSV11-Q_QBUS_memory
> >
> > It includes a table which says which chip each bit in the memory is
> stored
> > in (which is what one needs to fix one which is basically working, but
> has
> > some bad bits).
> >
> >
> > While working out that table, I ran into a hitch, which is a good part
> of why
> > it took so long. The hitch, when solved, revealed something mildly
> interesting.
> >
> > The hitch was in my process for finding out which bit was stored in
> which chip.
> > I whipped up a simple loop to store a word with a single '1' bit, and the
> > rest 0's; I set that running, and used a 'scope probe on the DIn pins to
> find
> > out which column of chips held bit 0, etc. So far, so good. I then
> looked on the
> > -Wr pin, to find out which row of chips held which banks.
> >
> > Not so good! There were pulses on -Wr for _all_ the banks, no matter
> which
> > address I tried to write to.
> >
> > Eventually I worked out what was going on: when writing data, the MSV11-Q
> > sends a 'write' signal to _all_ the banks, and selects the one to
> _actually_
> > use by use of the RAS signal. I'm not certain why DEC did this, but since
> > there is no explicit 'read' signal on the DRAM chip, and likely the data
> > outputs from all the banks are wire-OR'd together, use of RAS to select
> the
> > desired bank works for read, and also for write.
> >
> > Has anyone else seen this trick used anywhere else?
> >
> >       Noel
> >
>


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