VHDL / IBM SMS Data gathering and HDL Synthesis Update

Jay Jaeger cube1 at charter.net
Sun Jun 14 16:25:37 CDT 2020

Don't know if anybody much cares, but:

The HDL synthesis aspect of the SMS data gathering / HDL synthesis
application is coming along.  I can now handle:

- Oscillators (using a counter divider)

- Delay lines (using a shift register, so limited to a reasonable number
 of FPGA clock clock cycles, so, say 200 ns is not unreasonable (20 bit
shift register at 100 MHz).

- Recognition and consolidation of individual signals into a "bus" when
generating groups corresponding to a group of individual ALD sheets.
(The individual ALD sheets use the individual signal names as they
appear on the sheet).  A simple database table associates a given
individual signal with a bus, and identifies the bit in the bus that
corresponds to the individual signal.

So, I have not generated the IBM 1410 main oscillator, its main logic
clock and its I Ring - used to control instruction decode.  I have
synthesized the logic clock into an FPGA and run it (with a slowed down
1410 oscillator so I could see what was going on.)

Also, a word about VHDL - and the Xilinx Vivado.  While GHDL is useful,
I have found that Vivado is not slow at editing and *simulation*.  Silly
me - I got in the habit of synthesizing stuff before I tested it under
simulation - partly because I didn't know any better at first.  Vivado's
waveform viewer has some advantages (and disadvantages) compared to what
is available for GHDL.

I have also started exploring a piece of "intellectual property" I can
use - MicroBlaze - to allow my generated system to talk to my PC, via
TCP, for things like lights and switches.  (Kind of like how the Amdahl
machines used to use first DG Novas, and later little UNIX systems for
their consoles, giving them access to the internals of the machine.)

I knew MicroBlaze existed, but now I have actually played with it a bit
-- still learning.


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