LISP implementations on small machines

[Eric Smith]

On Thu, Oct 3, 2019 at 12:04 PM Guy Sotomayor Jr via cctalk <
cctalk at classiccmp.org> wrote:

> So does the PDP-11.  The 8 registers are mapped to the top 8 words of
> memory so you can do some quite interesting things.  It is also possible to
> run a (small) program in only the registers (e.g. no memory at all).
>

That's not an actual PDP-11 architectural feature, and it only works on the
KD-11B CPU (PDP-11/05 and 11/10). No other models can execute code from the
general purpose registers, or access the GPRs via a memory address. When an
instruction word is fetched from a GPR, the PC is only incremented by one,
because the 16-bit registers are at consecutive addresses, rather than
multiples of two as one would expect. The GPRs are not byte-addressable.

On all other Unibus PDP-11 processors made from TTL (i.e., not based on the
F11 or J11), the general-purpose registers can be accessed at the same
addresses from the console, but NOT from software.

Code can be executed from the MMU PAR registers on processors with 22-bit
addressing (11/23, 11/24, 11/44, 11/70, and J-11 based systems). These are
word registers at word addresses, so they don't have the increment-by-one
hack of the 11/05 executing from GPRs.