M7264 Troubleshooting

allison allisonportable at gmail.com
Wed May 29 11:40:20 CDT 2019

On 05/29/2019 07:17 AM, Noel Chiappa via cctech wrote:
>     > From: Josh Dersch
>     > how is the backplane in the H11 currently configured? (i.e. what boards
>     > are in what slots?)  Could the issue here be something as simple as a
>     > break in the qbus due to a misplaced board?
> He did mention that he had the console card in the slot next to the CPU, which
> I think is what you're referring to - but it shouldn't matter for ODT, which
> doesn't use interrupts, only programmed I/O.
> A QBUS system will work fine without continuity of grant (interrupt, DMA)
> lines to boards which only respond to DATI/DATO (memory, non-interrupt I/O,
> etc). Just for grins, I took my -11/03, and plugged the console card in a
> bunch of slots down, leaving several empty slots between it and the CPU, and
> it worked 'fine': ODT was fine, and it would run "BR ." programs fine, too.
> So unless there's actually a break in one of the 'broadcast' bus lines (e.g.
> BDALxx, etc) on that backplane, between the CPU slot, and the slot the console
> card is in, or something like that...
> I suppose it would be worth while checking BDALn, BSYNC and BDIN _on the
> console card_ (I'm not sure where he was looking at them, before) just to
> rule out the broken bus line possibility.
> One thing that's bugging me, though; he said "BDAL3-13 .. are all active and
> jump around in some manner". But for the ODT microcode loop trying to read the
> console CSR, i.e. 0177560, BDAL7 (0200) and BDAL3 (010) should be 0, i.e.
> un-asserted.
> So why are they jumping around too? Is this somehow related to the odd behaviour
> I was seeing on my machine with no console card, where the BDAL line was behaving
> in a way I couldn't understand?

BDAL, Bus Data and Address lines.  During the nominal cycle the address,
then strobe, then data (from ot to an addresses device or memory) and
controls asserted for the cycle type (ReadWord, Read ByteHigh,
ReadbyteLOW, WriteWORD and so on.  There are also transfers on the
same lines for interrupt vector and priority.

All that makes the BDAL lines busy...

Generally the LSI-11 is a bit stranger as it also does bus level
memory refresh for dynamic ram card that do not refresh themselves.
The contemporary memory cards did not self refresh and used the early
4K or 16K 16pin devices.  Memory used for 11/23 (f11) and later
by then self refresh on the local card level was the norm and cut
bus traffic load.

Many of the functions were replicated as part of the T-11 CPU.

> I'm going to look into that more, to try and understand what I'm seeing there,
> but it won't be today, which is 'crane day'!

Big tree!


>    Noel

More information about the cctalk mailing list