M7264 Troubleshooting

[Noel Chiappa]

Hi, sorry about the delayed reply; been dealing with this:

  http://ana-3.lcs.mit.edu/~jnc/jpg/backoak/WholeTreeS.jpg

The cranes arrive tomorrow...


    > I took a look at all the lines you mentioned. BDAL3-13, BDIN, BSYNC, and
    > BBS7 are all active and jump around in some manner.

Hmm. Well, that shoots down the simplest theory; that a CPU BDAL (or perhaps
BDIN) driver (technically, a transceiver) chip is bad; if you're seeing any
activity at all on a line, the driver must be working. So, either both console
cards have an issue, or something more complex is going on.

Here are some pictures to show you what you should be seeing, and what I'm
seeing with an LSI-11 with no console card. First, normal operation:

  http://ana-3.lcs.mit.edu/~jnc/tech/pdp11/jpg/BSYN-BDAL_OK.jpg

The top trace is BSYNC, the bottom BDAL10 (which should be asserted for
0177560, the console CSR's address; it's the 02000 bit). The timebase on this
one is 1 usec per division. As you can see, it's in a tight loop reading that
register.

The QBUS spec shows that for a DATI cycle, the DAL lines are set up before
BSYNC is asserted (falling edge here, since the bus lines are inverted).
BDA10 is indeed asserted (low) when that happens; shortly after it goes back
to 0 (high) so that device can put its data out on those lines. It stays high,
so that bit in the CSR must be 0.

OK, now a picture of the bus with no console card:

  http://ana-3.lcs.mit.edu/~jnc/tech/pdp11/jpg/BSYN-BDAL_NoCon.jpg

It's a bit hard to interpret what's going on here (note that the timebase is
much larger - 5 usec). The long assertion of BSYNC is undoubtly the CPU trying
to get the console CSR to respond, and eventually timing out.  Not sure what
the short assertion following it is - without looking at the ucode for the
ODT, there's no way to know what the CPU's doing.

Even harder to understand is what the BDAL line is doing. It looks like it's
un-asserted (0, i.e. +3V) on the falling (electrically - rising, logically)
edge of BSYN (which would be incorrect - see above). And then it hops around
while BSYNC is asserted, which makes no sense at all to me.


At this point, my best guess at the most likely cause of your problem (given
the 'all the lines are doing stuff') is that both console cards have
issues. Tomorrow, when I'm not outside, I'll try and look at some other BDAL
lines and see if they are doing the same thing with no console card in.

      Noel