jnc at mercury.lcs.mit.edu
Tue May 21 18:56:41 CDT 2019
> From: Mister PDP
Well, I verified that the LSI-11/2 should work in a Q22 backplane -
in the sense that the only pins it tries to talk to are standard
QBUS pins, and AF1/AH1 for SRUN. It doesn't drive BREF, which might
cause issues in later QBUS systems.
Although it's a different board from the LSI-11, it uses the same CPU
chip set, so it should give us some useful comparison data.
So after a certain amount of issues (see next), I got my LSI-11/2 working.
(It doesn't seem to work with Q18 memory, such as the MSV11-D. Attempts to
write 0 to memory from ODT wind up leaving the bits in the high byte set.
I have no idea why - anyone have any ideas? With Q22 memory, the symptoms
are even stranger; the system hangs with the 'run' light on - even with
the HALT switch on! Luckily I had an MMV11, and it worked OK with that.)
> I took a picture of the readouts for SRUN
Odd. On the LSI-11/2, with the machine stopped, 'run' was off, and the
output on AF1/AH1 was always high (i.e. not asserted).
I don't have any guesses as to what the behaviour of yours is about.
> Checking the BSYNC, it looks like there is life. It oscillates at
> 58.605 KHz, and has wider peaks than the SRUN signal.
The frequency is not as useful as plain timings - especially for signals
which don't have a 50/50 duty cycle. For example, on the -11/2, while in
the ODT console CSR read loop (below), BSYNC is asserted for 2.5 usec
(which sounds about right for a complete read cycle), then off for 1.0
Also, in the pictures, it's not clear which part of the cycle is asserted
(which, on the QBUS, is 0V - i.e. inverted) and which is idle (~3V). Is
this the actual bus signal we're seeing, with high being idle, zor on the
other side of an inverting receiver?
The image shows some timing numbers, but it's not clear that they mean.
E.g. above, it says "4.00 usec" - but is that per division, the whole
horizontal, what? Below, I see below "17.06 usec", and if that's the
rising edge -> next rising edge interval, that sounds like a bus timeout
> This signal does not respond to the Run/Halt switch being toggled,
> but I would assume that to be normal
Right; while in ODT the CPU is trying to read the console CSR, and
so you should see BSYNC cycling.
At this point, you might want to look at BRPLY, which will tell us
if the console is responding to the read of the CSR.
Also, I don't know if your /73 system has a KDJ11-A (dual width card, no
onboard console) or a KDJ11-B (quad width card, onboard console); if the
former, it might be worth swapping the DLV11 card into that system to
see if _it_ is working.
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