M7264 Troubleshooting

Brent Hilpert bhilpert at shaw.ca
Mon May 20 01:48:37 CDT 2019

On 2019-May-19, at 9:09 PM, Glen Slick via cctalk wrote:
> On Sun, May 19, 2019 at 8:05 PM Mister PDP via cctalk
> <cctalk at classiccmp.org> wrote:
>> After that, I decided to try and find out why the
>> Run/Halt light was not coming on when I hit the switch. Looking at the H11
>> schematics, the light relies on the SRUN signal coming off of the
>> backplane. The problem I am currently facing is I cannot find where the CPU
>> board generates the SRUN signal. If anyone who is more experienced that me
>> knows how the M7264 generates the SRUN signal, that would be wonderful.
> http://www.bitsavers.org/pdf/dec/pdp11/1103/1103_Schematics.pdf
> Page 27 of the PDF, LSI-11 CPU MODULE (K8) schematic
> Grid position B1, the SRUN L signal is driven on to the backplane bus line AF1.
> I have no idea how the logic works on the M7264 module that drives that signal.

It looks like the CPU chipset is putting a binary 'state action code' onto the
WMIB 18-21 lines (sources on page K2) during clock phase 3 (PH 3 H at gate E45.10).

The action code is decoded to 1 of 8 actions by E68.

Most of the states are latched by the subsequent flip-flops,
and those states are cleared or set by the action codes.

Except the SRUN (K8 SRUN L) action is not latched, so it probably appears as an
active-low heartbeat pulse with some periodicity when the processor is in run mode.
A low-going pulse during PH 3 every instruction cycle perhaps.

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