M7264 Troubleshooting

[allison]

On 06/08/2019 07:08 PM, Noel Chiappa via cctalk wrote:
> A follow-up to close out something:
> 
>     > OK, now a picture of the bus with no console card:
> 
>     > http://ana-3.lcs.mit.edu/~jnc/tech/pdp11/jpg/BSYN-BDAL_NoMem.jpg
>     [Note: image re-named, to correctly say what it's showing]
> 
>     > It's a bit hard to interpret what's going on here .. The long assertion
>     > of BSYNC is undoubtly the CPU trying to get the console CSR to respond,
>     > and eventually timing out.  Not sure what the short assertion following
>     > it is - without looking at the ucode for the ODT, there's no way to know
>     > what the CPU's doing.
> 
>     > Even harder to understand is what the BDAL line is doing. It looks like
>     > it's un-asserted (0, i.e. +3V) on the falling (electrically - rising,
>     > logically) edge of BSYN (which would be incorrect - see above). And then
>     > it hops around while BSYNC is asserted, which makes no sense at all to
>     > me.
> 
> So this makes a little more sense now.
> 
> This is actually showing a NXM cycle to main memory (apparently to address 0),
> hence the '0' on BDAL10. (The second assertion of BSYNC must be somehow
> associated with the NXM.) Apparently it doesn't even try to talk to the
> console card unless the memory is there OK; if it can't see the memory, it
> must just reset and try again.
> 
> Here:
> 
>     > http://ana-3.lcs.mit.edu/~jnc/tech/pdp11/jpg/BSYN-BDAL_NoCon.jpg
> 
> is a system with memory, but without a console. A very similar picture, but
> here BDAL10 _is_ '1', as expected.
> 
> 
> So the original picture did in fact indicate what the problem was - had I
> known enough to know how to interpret it! Schaeffer's Law strikes again!
> 
> Although I still don't understand why the LSI-11 wants to see main memory on
> the bus, in order for ODT to run. ODT doesn't use memory at all; ODT on the
> KDF11 CPUs will run without any memory.

ODT for the two systems are very different.  The LSI-11 ODT is microcode
in the base CPU MICOM set and very low level. Also the 11/2 cpu (dual
width is a bit differnt), KDF-11 the ODT is part of the higher level
code.  The larger cards (11/23 and 23+) boot to resident (ep)rom.

Also consider the difference between the restart/run between the two.
If memory serves The KDF11 requires enough ram to have a few of the key
addresses in low memory operational.

There is a lot going on with the LSI-11 as it also initializes internal
and external RAM. At the time memory nearly always dynamic and require
refresh cycles before it is "on line".

The manuals detail it well.


Allison

>       Noel
>