early PDP-11/45 info sought

[Fritz Mueller]

> On Jan 31, 2019, at 12:02 PM, Jay Jaeger <cube1 at charter.net> wrote:
> 
> The parity change in the CPU was to change parity errors from vectoring
> thru location 4 to vector through 114.

Yes, but also, there was apparently rework of logic feeding the CONF console flag and associated abort signaling.  Before the ECO's (as in my system) a UNIBUS parity error actually causes a machine halt, and not a trap.  (After the ECO's, FASTBUS memory apparently could still do this, optionally, but would then continue on to trap 114 after front panel CONT.)

Also, jumpers were added at some point to optionally disable detection of UNIBUS parity errors entirely.

  --FritzM.