Change in UNIBUS parity operation (Was: PDP-11/45 RSTS/E boot problem)

[Noel Chiappa]

    > Even better, it claims to be able to control whether the memory uses odd
    > or even parity! (How, for UNIBUS memory, I don't know - there's no way to do
    > this over the UNIBUS.

So this really confused me, as the UNIBUS spec says parity is wholly within
the slave device, and only an _error_ signal is transferred over the
bus. E.g. from the 'pdp11 peripherals handbook', 1975 edition (pg. 5-8): "PA
and PB are generated by a slave ... [it] negates PA and asserts PB to indicate
a parity error ... both negated indicates no parity error. [other
combinations] are conditions reserved for future use."

The answer is that originally the UNIBUS parity operation was _different_, and
that sometime around the introduction of the PDP-11/45, they _changed_ it, which
is apparently why Appendix E, about parity in the /45, says what it does!

I found the first clue in the MM11-F Core Memory Manual (DEC-11-HMFA-D - which
is not online, in fact no MM11-F stuff is online, I'll have to scan it all and
send it to Al); I was looking in that to see if the parity version had a CSR
or not (to reply to Paul Koning), and on the subject of parity it said this:
"The data bits on the bus are called BUS DPB0 and BUS DPB1." And there is
nothing else on how the two parity bits are _used_ - the clear implication is
that the memory just _stores_ them, and hands them to someone else (the
master) over the bus, for actual use.

Looking further, I found proof in the "unibus interface manual" - and
moreover, the details differ between the first (DEC-11-HIAA-D) and second
(DEC-11-HIAB-D) editions (both of which differ from the above)!

In the first, Table 2-1 has these entries for PA and PB: "Parity Available -
PA ... Indicates paritied data" and "Parity Bit - PB ... Transmits parity
bit"; at the bottom of page 2-4 we find "PA indicates that the data being
transferred is to use parity, and PB transmits the parity bit. Neither line
is used by the KA11 processor."

(Which explains why, when, after reading about parity in the MM11-F manual,
I went looking for parity stuff in the KA11 which would use it, I couldn't
find it!)

In the second, Table 2-1 has these entries for PA and PB: "Parity Bit Low - PA
... Transmits parity bit, low byte" and "Parity Bit High - PB ... Transmits
parity bit, high byte"; at the top of page 2-5 we find wholly different text
from the above, including "These lines are used by the MP11 Parity Option in
conjunction with parity memories such as the MM11-FP."

I looked online for more about the MP11, but could find nothing. I wonder if
any were made?

This later version seems to agree with that Appendix E. I tried to find an
early -11/45 system manual, to see if it originally shipped with MM11-F's,
but couldn't locate one - does anyone have one? The ones online (e.g.
EK-1145-OP-001) are much later.

It's also interesting to speculate about _why_ these changes were made; I can
think of several! :-)

      Noel