Motorola M88K books & user manuals (looking for)

[Carlo Pisani]

> I was never a fan of RISC architecture as does not fit the standard high
> level language model. Everybody wants a 1 pass compiler, thus the RISC
> model. If you are doing your own RISC model, you might consider a model
> that supports Effective addressing better since we have got the point
> where fetching the data is taking longer than processing it.

yup. I am a 68k programmer so I know what you mean.
the 68k is more comfortable to be programmed in assembly, and even the
EA modes (especially in the 68020 and CPU32) help a lot.

unfortunately, the 68K is very complex to be designed, and the first
68020 used microcode, which is a no-go for modern designs.

Arise-v2 comes doesn't have auto incrementer/post decrementer (aka
push pop and like), the EA model is basically minimalistic, but we
have a special instruction called "SLAC" which is extremely useful for
accessing a matrix's cell

SLAC means shift left and accumulate

in a matrix, a cell is usually accessed by a similar construct, so we have

EA = slac ....
load/store EA ...

yes, our demos will use a lot of matrices and convergences. Just for fun.

> The other thought is the pipeline seems has too high speed of a clock,
> what is the use a fast clock, if you got one or two gates of logic

For sure Arise-v2 will be implemented on a Spartan6 board clocked at
50Mhz for the core and 99Mhz for the DRAM controller, and won't use
the pipeline: it will be a multicycles not-pipelined CPU. This because
the pipeline introduces a lot of hazards that need to be solved, and
this will be our "phase two".

First, we need to design and test the ISA on a software simulator in
order to check if it's coherent, then, once the ISA is stable, we will
put it into a simple hardware implementation, and at that point, we
will be able to design a branch prediction etc.

Arise is a "learning toy", anyway. All the serious job is done on the RISC-V.

On DTB we have a list of RISC-V boards for all the tastes and
different costs: ... RISC-V on ASIC chip, RISC-V on FPGA, etc ...

(1) http://www.downthebunker.xyz/wonderland/reloaded/bazaar/viewtopic.php?f=3&t=192&sid=412586cc3d070058ee904a71aceb9e76

We will try to keep the list updated. Probably someone on our team
will also buy a RISC-V board. Currently, we are all working on
simulators.

> Good luck with your design.

thanks!