Rayethon Computer AN/FYK9 CMI Store 33

[Zane Healy]

> On Sep 25, 2018, at 9:21 AM, Chuck Guzis via cctalk <cctalk at classiccmp.org> wrote:
> 
> On 09/25/2018 08:45 AM, Christian Corti via cctalk wrote:
>> On Mon, 24 Sep 2018, Chuck Guzis wrote:
>>> How about some 22-bit or 13 bit architectures?
>> 
>> How about our Dietz MINCAL 523? 19 bit architecture, memory is 20 bits
>> with parity. Microprogrammed machine, microcode within normal address
>> space, mixed twos-complement and sign-magnitude arithmetic. Completely
>> reverse-engineered due to lack of information :-))
>> 8K core memory, microcode and boot loader stored in foil ROMs (similar
>> to wire rope ROMs).
> 
> I was wondering if anyone would rise to the challenge.  In fact, some
> Harvard-architecture MCUs have unusual *instruction* word lengths.
> 
> I think the PB250 was 22/44 bits and, of course, there was a whole horde
> of 36-bit mainframes, some extending well into the 1980s, as well as
> other systems with multiples of 6 bit lengths.
> 
> How many of today's ISAs are *not* byte-addressable nor implement a
> stack?  I'm somewhat curious as to how HLLs have influenced our thought
> regarding architecture.
> 
> --Chuck
> 

I’m trying to remember if the Harris Minicomputers were 22-bit or 24-bit, I think they were 24-bit.

Zane