i860: Re: modern stuff

[Eric Korpela]

The i860 did find some use in the radio astronomy world.

Here's an excerpt from the 1998 annual report for the Arecibo Observatory...
--------------
Telescope pointing and realtime data acquisition are controlled using a
network of VMEbus single-board computers running the VxWorks operating
system kernel. Custom-built data acquisition devices (‘‘backends’’) include
(1) a general purpose A/D system capable of sampling four analog channels
at up to 10-MHz rates with programmable resolutions of 1 to 12 bits per
sample per channel, (2) an ~interim! 50-MHz, 4096-lag Spectral Line
Correlator with programmable bandwidth from 195 kHz to 50 MHz, (3) a 50-MHz
Radar Decoder, ~4! a 100-MHz Spectral Line Correlator being developed, (5)
a 10-MHz bandwidth Pulsar Search/Timing Machine with up to 256 channels,
and (6) a wideband continuum/polarimetry instrument being developed. An S2
VLBI system is also available. Additional realtime signal processing
capability is provided by four Skybolt i860-based VMEbus single-board
computers with 240 MFLOPS peak combined capacity.
--------------
Remember when 240 MFLOPS was a lot?

I also seem to recall that the SERENDIP III SETI spectrometer used i860 and
Austek A41102 FFT processors.  I'm pretty sure SERENDIP IV used i960 and
Xylinx FPGAs to do the FFTs.  I'll look at the boards tomorrow.



On Mon, Oct 29, 2018 at 9:56 AM Ken Seefried via cctalk <
cctalk at classiccmp.org> wrote:

> >the i860 found at least a little niche on graphics boards, so somehow
> >not a complete failure ;-)
>
> I'd be mildly surprised if Intel ever made enough from selling i860s
> as GPUs to cover the cost of developing and marketing them.  At the
> time, Intel was pushing them as their RISC processor, and put a lot
> into the program.  Going to take over the world and all that.  Maybe
> not a 'complete' failure...just mostly.
>
> From: Chuck Guzis <cclist at sydex.com>
> >On 10/26/18 6:10 AM, Gordon Henderson via cctalk wrote:
> >
> >> However it was a royal PITA to code for although a 32-bit CPU, it would
> >> read memory 64 bits at a time (actually 128 IIRC to satisfy the cache),
> >> with half that 64-bit word being an instruction for the integer unit and
> >> half for the floating point unit, so you effectively had to build a
> >> floating point pipeline by hand coded instructions, so 8 (I think)
> >> instructions to load the pipeline, then each subsequent instruction
> >> would feed another value into the pipe, then another 8 at the end to
> >> empty it. Great for big matrix operations, rubbish for a single add of 2
> >> FP numbers.
> >
> >My impression of the i860 was that it might have been fun for about 2
> >weeks for which to code assembly, but after that, you'd really start
> >looking hard for an HLL to do the dirty work for you.  While there's a
> >sense of accomplishment over looking at a page of painfully
> >hand-optimized code that manages to keep everything busy with no
> >"bubbles", you begin to wonder if there isn't a better way to spend your
> >life.
>
> It wasn't fun for the whole 2 weeks.  And the i860 is Yet Another
> example of Intel claiming their compilers were going to be so smart
> that all the architectural complexity/warts will never be noticed.
> Wrong, and they didn't learn and said the same thing about Itanium.
> The interrupt stall issue that Gordon pointed out was so bad they were
> basically relegated to single-task software in the end.
>
> KJ
>


-- 
Eric Korpela
korpela at ssl.berkeley.edu
AST:7731^29u18e3