70's computers

[Paul Koning]

> On Oct 24, 2018, at 9:01 AM, Noel Chiappa via cctalk <cctalk at classiccmp.org> wrote:
> 
>> From: Paul Koning
> 
>> A lot more comes from the CPU architecture. The instruction set, of
>> course (arguably the first RISC).
> 
> An observation about RISC: I've opined before that the CISC->RISC transition
> was driven, in part, by the changing balance of CPU speed versus memory
> speed: with slow memory and fast CPUs, it makes sense to get as much
> execution bang out of every fetch buck (so complex instructions); but when
> memory bandwidth goes up, one needs a fast CPU to use it all (so simple
> instructions).
> 
> It occurs to be that the same balance probably applies to memory _size_. When
> memories are small, one wants dense code (which probably means CISC); only
> with larger memories does RISC, with its less-dense code, make sense.

That sounds reasonable.  But what does that say about the CDC 6000 series?  It's RISC, essentially, running on expensive and fairly slow memory.  (Fast bandwidth due to 32 way interleave, but roughly 8 cycles access latency.)  I think the magic is that the instruction encoding is very efficient, so you get the execution benefits of RISC without  the space penalties.

	paul